1. Field of the Invention
The present invention is directed to providing valid random input sequences to be applied to integrated circuit chips and chip systems to test functional logic circuitry of the chip or in the system. The present invention provides a coding method for guiding simulation of highly optimized pipelines in Memory Control Units, I/O Adapters, Processor Interconnect Units, etc.
2. Description of Background
Previously, random input sequences were used for guiding the simulation of highly optimized pipelines. However, random input sequences failed to effectively provide coverage of unique window and corner conditions. Subsequent quasi-random, biased approaches utilized optimization criteria that increased coverage only linearly and were not exhaustive.
Formal approaches required extensive assertion coding for state-space exploration and were limited in scope to extremely small circuits. Thus, a clear need exists to eliminate the ineffective sequences that are generated using biased random techniques, while also avoiding the cost and size limitations of formal approaches.